1. Field of the Invention
This invention relates to a cache memory consisting of a small capacity, high speed memory provided for reducing the access time of the main memory.
2. Description of the Prior Art
A cache memory is generally provided between a CPU (processor) and a main memory for the purpose of reducing the access time when accessing the main memory. The CPU can access the cache memory at a high speed. The presence in the cache memory of data to be accessed is referred to as cache hit, while there is no data to be accessed is referred to as cache not hit. The data which has not recently been accessed (referred to) from the CPU although it has been stored in the cache memory, is expelled due to data which newly become necessary, and new data from the main memory is used to replace data in the cache memory.
At this time, the process where data is read out or written in the cache memory or main memory, is done through advanced control, and the speed of data processing by the CPU is increased through pipeline control which is done for parallel process of a plurality of commands.
FIGS. 7 and 8 illustrate the construction of a prior art cache memory. FIG. 7 is a block diagram showing cache memories 2, 2a, 4 and 4a as high speed buffer memory used between the CPU and main memory 12, and FIG. 8 is a detailed block diagram showing a system controller shown in FIG. 7. The operations in the cache memory of such construction are roughly classified into two kinds, i.e., AA cycles AA1, AA2 and AA3 of the address description command corresponding to instructions REQ1, REQ2 and REQ3 and DA cycles DA1, DA2 and DA3 of data designation commands, as shown in FIG. 5.
In the AA cycles a request signal REQ is supplied from the CPU to a bus line 25b of the cache memory, and address data (logical address) is supplied to a bus line (A-BUSS) 22. The address data has to be converted into actual address of the main memory due to imaginary addresses in the imaginary address space. In the MAP circuit 1, the, logical (imaginary) address is converted by mapping into the physical (real) address as shown in FIG. 6, and the comparator 3 or 3a checks whether the outputs of the MAP circuit 1 and address array 2 or 2a coincide with each other in the physical address.
In the DA cycle the data array 4 or 4a as the subject is detected according to physical address coincidence data obtained after the AA cycle completion, and operations of completing the reading or writing with respect to this data array are performed.
As shown in FIG. 5 the advanced control of the commands REQ1.fwdarw.AA1.fwdarw.DA1 concurrently with the commands REQ2.fwdarw.AA2.fwdarw.DA2 which are subsequent processes timewise constitutes a pipeline control of the cache memory.
The prior art cache memory process operation will be explained according to the timing chart shown in FIG. 9. First, the clock is a reference clock signal in the cache memory. Now, when a request signal REQ1 is supplied from a CPU (not shown) to a bus line 25b of the system controller 21, the system controller 21 supplies a response to the CPU through the bus line 25c. In other words, an acknowledge signal ACK1 is provided to enter the AA1 cycle. At this time, a logical address is supplied to the MAP circuit 1 through a bus line 22.
The request signal REQ1 is also supplied to the address arrays 2 and 2a to provide a physical address stored therein. This address is compared with the converted physical address from the MAP circuit 1 in the comparator 3 or 3a. The address arrays 2 and 2a, comparators 3 and 3a and data arrays 4 and 4a are provided in pluralities in order to increase the capacity of the cache memory.
When a coincidence cache hit signal is supplied from the comparator 3 or 3a to the decoder 8, the address of the subject data array 4 or 4a corresponding to the address decoded is set in the data array address register 9.
This cache hit signal is supplied to the decision circuit 6 and rendered to be designation data with reference to the physical address from the address array 2 and 2a to be stored in the replace array 5. When the cache not hit signal to be described later is supplied from the comparator 3 or 3a, the designation data serves to make a decision as to whether the data of the data array 4 or 4a is to be replaced with the data of the main memory 12.
The data of the data arrays 4 and 4a accessed by the data array address register 9 enters a parity checker 20 for parity check. Also, it is selected by the selector 16 to be supplied to the data register 18 and then set in the data bus 23.
From the instant when the address due to the request signal REQ1 is set in the data array address register 9, the next request signal REQ2 is supplied to the address arrays 2 and 2a, and the logical address signal is supplied to the MAP circuit 1. Then, comparison is done in the manner as described above. This time, the cache not hit signal is provided from the comparators 3 and 3a. This signal is supplied together with the output of the replace circuit 5 to the decision circuit 6. As a result, the data array 4 or 4a, whose data is interchanged with the data of the main memory 12 is determined, and the subject address is set in the address register 9.
While the cache hit signal is being supplied from the comparators 3 and 3a to the decoder 101 of the system controller 21, the terminal 32 of the decoder 101 is held at "high" by REQ and CODE signals supplied to the bus line 25a to set the flip-flop 103, to provide the read-out designation execution signal DAF. This command DAF is supplied to the data arrays 4 and 4a, and the read-out data is set on the data bus 23 as noted above.
Likewise, when the request signal REQ2 is supplied, an acknowledge signal ACK2 is provided from the system controller 21. This time, a cache not hit signal is supplied to the decoder 101, whereby the terminal 33 of the decoder 101 is rendered to be "high" to set the flip-flop 104, thus providing the main memory read-out designation execution signal MMF.
The MMF signal having passed through the OR circuit 109 causes the signal BRQ to provide from the flip-flop 108 and also causes the negative logic signal MEMF to provide from the negative logic signal MEMF. This signal BRQ provides a memory request to the memory bus controller 11 to obtain the right of use of the memory bus 24 and also provides an access signal for data reading to the main memory 12. The signal MEMF shows that the main memory 12 is being accessed, and at the same time the gate 110 is controlled to inhibit the supply of the signal ACK from the flip-flop 102 to the CPU so as not to receive the signal REQ.
At the instant when the response BACK with respect to BRQ is returned from the memory bus controller 11 to the flip-flop 108, BEQ is reset. At the instant when the signal SYNC is returned from the memory bus controller 11, MEMF of the flip-flop 107 is reset. The signal SYNC is a synchronizing signal indicating that data is being provided from the main memory 12 to the memory bus 24 and that data has been conversely stored from the memory bus 24 to the main memory 12. During this time, i.e., during the period, during which BRQ is reset and SYNC is set, the AND gate 114 provides the signal BKWR for altering the data of the address arrays 2 or 2a and data arrays 4 or 4a (necessary for the renewal of the not hit). In this way, the address from the address register 10 is stored in the address array 2 or 2a, and data from the memory 12 on the memory bus 24 is supplied to the data array 4 or 4a.
When the MEMF is reset the system controller 21 receives the next REQ 3 and supplies ACK3 to the CPU for the execution of the operation of each of the cycles AA3 and DA3.
In the timing chart shown in FIG. 9, FIGS. 1 to 3 designate cycle orders of AA1, DA1, AA2, DA2, etc. When a data parity error is detected in the parity checker 20 during the DA1 cycle of REQ1.fwdarw.AA1.fwdarw.DA1, the signal TRAP is provided from the trap generation circuit 26. The CPU proceeds to the abnormality processing and machine check processing.
When the flow of FIG. 10 is arranged, if there is REQ in a step P1, a check is done in a step P2 as to whether there has been a hit in the address arrays. If there is no hit, a step P3 is executed, and for the rewriting of the data array the data of the block unit is taken out from the main memory, and this data is loaded while expelling the old data. When there is a hit, a step P4 is executed, in which data array is read out, and in a step P5 the parity error check is done. If there is an error, a trap signal is generated in a step P6, a trap process is executed in step P7, and a machine check process is done in a step P8.
In the prior art cache memory, when a parity error is generated in the data array, the machine check process is given preference, the next cycle operation of the pipeline control is interrupted, so that it is impossible to make use of the function of the high speed processing cache memory.